Burroughs Medium Systems/V-Series

NOTE: This is an incomplete work-in-progress. Send questions, comments or updates to vseries at lurndal dot org.

The Burroughs (now Unisys) medium systems line descended directly from the Electrodata 300 series business computer systems. Developed at the same time as the famous Burroughs B5000 series systems, the medium systems line (B2x00, B3x00 and B4x00 series) was designed as a general purpose computer system for business data processing. Key characteristics of the architecture include Binary Coded Decimal (BCD) arithmetic on variable length operands up to one hundred digits in length, nibble-level addressability and high-level language support. Primarily designed to efficiently execute COBOL programs, the relatively high-level instruction set implements many common COBOL verbs with a single instruction. Unusually for architectures of this era, very high-level instructions for searching, data display and data translation were included in the core instruction set.

The medium system line is the direct descendent of the Electrodata systems.

From Computers and Automation, January 1970 (Numbers estimated by C&A, Burroughs refused to give information to C&A).

Type FIrst Installation Monthly Rental In USA Outside USA Worldwide Order Backlog
205 01/1954 USD4,600.00 25-38 2 27-40 No longer in production
220 10/1958 USD14,000.00 28-31 2 30-33 No longer in production
B100 08/1964 USD2,800.00 90 13 103 No longer in production
B200 11/1961 USD5,400.00 370-800 30 440-870 31
B300 07/1965 USD9,000.00 180-370 40 220-410 150
B500 10/1968 USD3,800.00 0 0 0 70
B2500 02/1967 USD5,000.00 52-57 12 64-69 (1974: 400) 117 (1974: 30)
B2700 08/1972 USD4,000.00-USD10,000.00 35 16 51
B3500 05/1967 USD14,000.00 44 18 62 (1974: 857) 190 (1974: 110)
B3700 11/1972 USD12,500.00-USD30,000.00 17 6 23
B4700 10/1971 USD14,000.00-USD90,000.00 78 26 104
B5500 03/1963 USD23,500.00 65-74 7 72-81 8
B5700 12/1970 USD32,000.00 (1974) 27 8 35 22
B6500 02/1968 USD33,000.00 4 0 4 60
B6700 08/1972 USD30,000.00 (1974) 55 26 81
B7500 04/1969 USD44,000.00 0 0 0 13
B7700 02/1972 USD85,000.00 (1974) 1 0 1 4
B8500 08/1967 USD200,000.00 1 0 1 5

Burroughs B2500/B3500

In 1956 the Burroughs corporation entered the business computer market by purchasing the Electrodata corporation. The Pasadena plant, while marketing and selling the Electrodata 200 and 300-series systems (now as the Burroughs B2x0/B3x0), began development of the B5000 series and the B2500/B3500 series computer systems.

The B2500/B3500 was announced in March, 1966, Designed with the explicit idea of being the target of a COBOL compiler. (Quoting Dave Dahm). The systems were rented for between USD4500 and USD20,000 per month. Shipping began 1Q67. Magnetic core memory of 10000 bytes to 150,000 bytes was available with a 2 microsecond cycle time on the B2500 and a 1 microsecond cycle type on the B3500 for each two bytes accessed. Estimated performance was 1.5 times the IBM 360/30. A B3500 could be configured with from one to twenty I/O channels. The processor included what today would be called cache memory with an access time of 150ns. Called address memory, it started at 24 16-bit words and could be expanded to 120 16-bit words.

The central processors incorporated extremely fast read-only storage. This storage device is wired with interpretive routines which are executed with a 50 nanosecond cycle time. These routines are called microprograms. The great advantage of microprograms is that various different routines may be wired in, allowing the emulation of other systems. This same technique was used by IBM in achieving compatibility between System/360 and the 1400/7000 series computers. Burroughs used this emulation technique to emulate its own 200 and 300 systems as well as the IBM 1401 series machines.

Burroughs offered two operating systems: the Basic Control Program (BCP) for one-at-a-time batch processing and a more sophisticated Master Control Program, patterned after that of the B5500, which supported multiprogramming. Under MCP, a B3500 could process up to 16 programs simultaneously.

Burroughs saw the IBM 360/30 and 360/40 as the principal competition for the B2500 and B3500, so the company decided to make their i/o systems IBM-compatible by using IBM's EBCDIC data code and many IBM file structures. There was no attempt at machine language compatibility (the strategy of RCA), but Burroughs did provide simulators for IBM's older 1401 computers. For its own customers there was a translator which would convert B300 assembler programs to the B2500 or B3500. Burroughs was successful in selling B3500s to military customers. In December 1967, the company won a $60 million contract to supply 150 of them for the U.S. Air Force base logistics project. The contract had originally been awarded to IBM, but the Department of Defense re-evaluated the bids after a protest by Honeywell. Burroughs also sold 43 to the U.S. Navy Systems Command (in 1971) and four modified verions to the U.S. Army for a mobile communications system. In all, 990 B3500s were delivered to civilian and military customers.

System Style Total Shipment
B2501 191
B3500 1007

Some text in this section was copied from the Unisys History Newsletter, Volume 3, Number 5 (copyright 1999 George Gray). Other parts of the section were derived from Computers and Automation, April 1966 http://bitsavers.trailing-edge.com/pdf/computersAndAutomation/196604.pdf.

B2500/3500 Introduction Advertisement, page 1 B2500/3500 Introduction Advertisement, page 2

Burroughs B2700/B3700/B4700

The next member of the Burroughs Medium Systems family was the 700 series systems. The B4700 being the largest of the medium system line at the time. Characteristics and pictures of the x700 family needed here.

Circa 1972, Burroughs also brought out new machines for its medium series: the B2700, B3700, and B4700 to take the place of the B 2500 and B3500. The new models could run existing B2500/B3500 programs without change. The B4700, which was twice as fast as the B3500, had from one to four CPUs, and the virtual memory capability was standard. Prices for the B4700 ranged from $650,000 for a one-CPU model up to $4,500,000 for four CPUs. The old batch BCP operating system was dropped, and the multiprogramming operating system was enhanced to handle up to 80 programs and renamed MCP V. The new File Protect Memory feature allowed multiple programs to access the same data file simultaneously in a fashion parallel to the database management systems of larger computers. Starting with the B4700, Burroughs decided to follow the example of the large systems and not provide an assembler in the medium series.

The above paragraph is also from the Unisys History newsletter (copyright 1999 George Gray). When George refers to four CPU B4700's, he's referring to a cluster of four B4700 systems using shared disk, not a multiprocessor B4700.

System Style Total Shipment (As Of 1976)
B2700 25
B3700 572
B4700 545

The B4700 added the following features to the architecture:

Burroughs B2800/B3800/B4800

Following the Bx700 series systems was the Bx800 series (sometimes known as MS-2?). These systems added faster processing, new I/O controls and more main memory capacity (The B4800 could support a full megabyte of main memory allowing access to two million digits). Characteristics and pictures needed here. MCPVI ran on the 800-series systems.

  • B2805
    • 3Mhz CPU, 200kd memory
    • DLPs for DISK, PRN, CRD, MTP
    • Up to 16 Channels (2 base cabinets)
    • $100,000 ($14,100 per 500kd memory extra)
  • B2835
    • 3Mhz CPU, 250kd memory
    • DLPS for DISK, PRN, CRD, MTP
    • Up to 24 Channels (3 base cabinets)
    • $135,000 ($14,100 per 500kd memory extra)
  • B3805
    • 4Mhz CPU, 500kd memory
    • 500ns cycle-time to memory for 16-bits (4 digits)
    • $175,000 ($30,000 per 200kd memory extra)
  • B3845
    • 4Mhz CPU, 1Md memory
    • $230,000 ($28,000 per 500kd memory extra)
  • B4885
    • 8Mhz CPU, 1000kd memory
    • Upgradable to 2000kd memory (1Megabyte)
    • $390,000 ($30,000 per 200kd memory extra)

Burroughs B2900/B3900/B4900

In the early 1980's, the penultimate members of the Burroughs medium systems line were developed. The B4955 was the high-end model in the 900-series family and provided access of up to twenty million bytes (forty million digits) of memory. MCPIX ran on the 900-series systems.

B2925, B2930, B3955, V310, B4925, V340, B4955, V380, V510, V530, V560, V410, V430, V460 were all developed.

Unisys V-Series

In the middle 1980's, the Burroughs Corporation purchased the Sperry Corporation and formed the Unisys Corporation. Coincident with this purchase, the Medium systems line was renamed as the Unisys V-Series, with the V300 family derived from the B4955. The first multiple processor machine in the medium-systems/V-Series family was designed, built and sold as the V500 (V510, V530 and V560). The V400 series systems followed. The V400 systems used the same hardware design as the V300 systems, except each 24” by 18” circuit board was reduced to a single gate-array significantly shrinking the footprint of the mainframe. The V4x0 series included a two processor version, unlike the uniprocessor V300 series.

The first V500 systems were shipped in 1987 (BAC in Brussels was a field test customer). The V560 was introduced in 1989.

here are still v-series systems running as of mid-2009 including a V380 (decommissioned 2010, moved to the Living Computer Museum in 2013).

The V430 started shipping in March, 1990 and sold for $314,252 with 2.6GB disk storage. The V410 started shipping in June, 1990 and sold for $164,236 with disk storage (amount not specified).

V3x0/V4x0 Overview
V5x0 Overview

Relative Performance Between Generations

A2 Mix A1 Mix
B2800 28 1.0 N/A N/A 1.0 N/A N/A
B3800 34 1.30 N/A N/A 1.30 N/A N/A
B4800 66 2.56 N/A N/A 2.56 N/A N/A
B2925 34 1.08 1.22 N/A 1.14 1.23 N/A
B3955 50 1.60 1.81 N/A 1.73 1.88 N/A
B4925 (V340/IX) 76 2.45 2.82 N/A 2.64 2.94 N/A
B4955 (V380/IX) 120 3.77 4.35 N/A 4.19 4.68 N/A
V340 76 N/A N/A TBD N/A N/A TBD
V380 120 N/A N/A TBD N/A N/A TBD
V510 250* N/A N/A TBD N/A N/A TBD
V530 460* N/A N/A 16.8* N/A N/A 18.0*
V560 830* N/A N/A TBD N/A N/A TBD
V580 1100* N/A N/A TBD N/A N/A TBD
V590 1290* N/A N/A TBD N/A N/A TBD
Note Entries marked with an asterisk were predicted values from the V500 System Product Specification (1993 5162 Rev. C) Page 17.

The A1 MIX is made up of the following types of programs:

  • Calendar Printing Program (COBOL74)
  • COBOL 74 Cross Reference
  • Document Editor (COBOL74)
  • Student Course Selection Program (RPG)
  • Matrix Inversion Problem (RPG)
  • DMS Database Load
  • DMPALL Disk to Disk transfer

The A2 MIX is based on a study of the customer workload at large Medium Systems sites. The study consisted of customer visits, user surveys, and system run log analysis. The mix consists of programs representative of these customer workloads:

  • On-line Banking Simulator
  • COBOL 74 Cross Reference
  • Document Editor (COBOL74)
  • Factory Material Requirements Planning
  • Grocery Warehouse Inventory (Forte 2)
  • DMPALL Disk to Disk Transfer
  • Treasury Tax and Loan System


V-Series Documentation

Central Processor

I/O Subsystem

The I/O Subsystem is a system wherein a type of intelligent interface control unit, designated as a Data Link Processor (DLP), is used, and wherein each DLP, while performing the same basic functions, is specifically oriented to control and handle data transfers to and from a specific type of peripheral terminal unit. For example, a basic DLP would be adapted for each specific instance to handle a card reader, a disk unit, a train printer, or other special type of peripheral unit. The DLP's are placed in groups, typically, of up to eight, to form an DLP Base Module.

In the I/O Subsystem using the Data Link Processors, the Main System (of Processor and Main Memory) is also provided with a unit called an Input-Output Translator unit (IOT) which becomes part of the Main System and provides an interface between the Main System and another distribution-control interface designated as “Distribution Card Unit” which handles a Base Module, (a group of Data Link Processors) and which connects a selected individual Data Link Processor into the DLP I/O Subsystem.

The Data Link Processor's (DLP's) are organized in groups of eight called the DLP Base Module each of which has a single “Distribution Card Unit” which provides the interface between the Input-Output Translator, IOT, of the Main System and the eight DLP's of any given Base Module. Each Base Module also carries a Maintenance Card unit which can provide all maintenance and checking functions for the group of eight DLP's of the Base Module. Each Base Module is also provided with one common “termination Card Unit” which provides common clocking functions for all the DLP's of the group and also provides proper terminations for the transmission lines which connect the various DLP's, the Distribution Card, and the Maintenance Card of that particular Base Module.

The IOT of the Main System works in a unique relationship with the Distribution Card Unit of the Base Module of the DLP's in the DLP I/O Subsystem, serving to setup data-transfers between the peripheral units and the Main Memory in a fashion that does not burden the Central Processor and which permits concurrent data-transfer operations to occur between any number of peripheral units and the Main Memory. This is facilitated by the use of a record-length buffer memory in each DLP. The data-transfer cycle is accomplished using complete data message-blocks which thus prevent “access errors” from occurring.

The IOT on all V-Series systems, depending on model may be configured to connect to from four up to eight Distribution Cards, supporting up to 64 DLP's,

The V-Series addresses each DLP using a four digit BCD value known as a channel number. The first two digits of the channel number must be zero, the third digit designates the Base Module (Distribution Card) and the fourth digit designates the DLP within that Base Module. The higher the Base Module number of DLP number, the higher the DLP priority. The DLP at channel 0077 (the eighth DLP in the eighth Base Module) has the highest priority, while channel 0000 has the lowest priority (the first DLP in the first Base Module).

I/O Processor (IOP) / I/O Translator (IOT)

The Input/Output Processor transfers data between memory and peripherals concurrently and independently of the Central Processor, maximizing throughput and efficiently managing up to 32 separate I/O channels on the V310 and V340 systems and up to 64 separate I/O channels on the larger-scale V380 system and V5X0 systems.

The Data Link Processor, (DLP), is a device which upon receipt of a Command Descriptor (C/D) from the Main System, via the IOT, establishes a communication path to a selected peripheral unit. Once this path is established, the DLP accepts data from or passes data to, the peripheral device. Since each DLP has a “data buffer” (typically 256 words), then data can be transferred to and from the peripheral device at the comparatively low speed rate of the peripheral device; then, when the buffer is full, the data can be transferred to the central Main System at the highest rate permitted by speed of the Main Memory. Thus, a unique interworking relationship exists between the IOT (Input-Output Translator) of the Main System and the DLP, which is the interface control between the peripheral units and the Main System. Further, a unique working relationship exists between each DLP and the Distribution Card Unit of its Base Module, which interfaces a given DLP to the IOT of the Main System. The Distribution Unit not only provides for interconnection of the Main System to a selected DLP but also regulates priorities among DLP's for the access to Main Memory.

With the release of the 3.0 version of MCP/VS, a single DLP can now have one operation in process simultaneously for each connected peripheral (e.g. for a disk or magnetic tape controller with a string of drives), unlike prior releases of the MCP/VS and MCP/IX operating systems which supported only one single outstanding I/O operation per channel at any given time.

The DLPs contain integrated data buffers that can accommodate each peripheral family and efficiently transfer data at high speed through fixed record length blocks. Most DLPs have at least two data buffers. While one buffer is used by the sending device, the other buffer is unloading to the receiving device. The buffers are alternated, or “ping-ponged”, until the entire message is received to minimize I/O interruption to the central system and enhance overall efficiency and productivity of the Host.

Data transfer between DLPs and the central system is performed at the Message Level Interface rate of eight million bytes per second.


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