The Burroughs Medium Systems (V-Series) line of mainframes used a relatively high-level machine instruction set to implement an architecture supporting two and three-operand instructions. Operands range in size from one to one hundred units in length, with a unit consisting of either one 4-bit digit or an 8-bit byte. Special bulk movement instructions (such as MVW (Move Words)) provide the ability to move up to 40,000 digits in a single operation optionally translating the data while it is moved (see TRN (Translate)), or clearing the data source region after the data has been moved (see MVC (Move Words and Clear)).
There are three data representations used by the processor:
All multi-unit values are stored in big-endian form with the most-significant unit (MSU) at the lowest address unless specifically noted otherwise.
Conversion between signed and unsigned 4-bit representation and 8-bit representation is accomplished automatically during execution of instructions. When an source operand to an arithmetic instruction uses 8-bit UA representation, the zone digit (high-order 4-bits) of the 8-bit unit is ignored. When a destination operand to an arithmetic instruction uses 8-bit UA representation, the zone digit (high-order 4-bits) of the 8-bit unit is set to the EBCDIC Numeric Zone digit value hexadecimal F.
Data is interpreted in units of 4-bits (one digit). The sign is interpreted as a sesparate and leanding 4-bit unit. The 4-bit code is interpreted by the processor as follows:
|4-bit Code||Digit||Sign Code|
|1010||A (Undefined *)||+|
|1011||B (Undefined *)||+|
|1100||C (Undefined *)||+|
|1101||D (Undefined *)||+|
|1110||E (Undefined *)||+|
|1111||F (Undefined *)||+|
[*] The hexadecimal digits A through F are hereafter referred to as undigits. Use of undigits in an arithmetic operand, except for the sign digit, will cause an Invalid Arithmetic Data fault (see Compatibility Notes A.16).
When the result of an operation is signed numeric SN, the sign digit is stored at the lowest address followed by the digits of the result starting with the MSU. The sign digit for a negative result will be the bit pattern 1101 (hexadecimal D) and the sign digit for a positive result will be the bit pattern 1100 (hexadecimal C). For input operands any value other than the bit pattern 1101 (hexadecimal D) in the first digit of the operand will be interpreted by the processor as a positive sign, although programmers are encouraged to use the value C as the sign digit for any positive value.
Data is interpreted in units of four-bits (one digit). Unsigned data fields are assumed to be positive.
Data is interpreted in units of eight-bits (one byte or one character).
The internal representation of alpha data is in the Extended Binary Coded Decimal Interchange Code (EBCDIC).
Eight-bit data is considered unsigned except in the case of the Move Alpha (MVA), Move Numeric (MVN) and Edit (EDT) instructions. Additional details are given in the description of these instructions.
Alphanumeric comparisons are binary and thus the (low-to-high) collating sequence for EBCDIC is symbols → alphas → digits.
Most instructions operate on memory directly. There are no general purpose registers, but there are seven index registers that may be used for operand address indexing.
The first one hundred digits of memory area zero has a number of fields with special meaning, including containing index registers one through three and the top-of-stack pointer.
|Address||Size||Representation||MCP/User Data Area||Kernel Data Area|
|0||40||UN||Indirect Field lengths at address 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30, 32, 34, 36, 38|
|8||7||SN||Index Register 1|
|16||7||Index Register 2|
|24||7||Index Register 3|
|38||2||UN||Scan Result Storage for SDE, SDU, SZE, SZU|
|40||6||Top of Stack pointer (see ASP, NTR, EXT, VEN, RET)||Kernel Stack Pointer|
|46||2||Breakpoint Bit pattern (see HBK)|
|48||2||Edit Table Entry 0 - 7 (see EDT)||Halt Execution Digit (48), Internal I/O Mask (49)|
|64||2||Trap enable (FF)|
|72||10||Unused||Processor Result Descriptor (R/D) Storage Area|
|94||6||ARM address (see ARM BCT)||Kernel Interrupt Branch Address|
|6000||7||SN||Application Usage||Head of Ready list pointer|
|6008||7||Current Task Reinstate List Pointer|
|6024||8||Instruction Interrupt Cause Descriptor|
|6032||8||Instruction Interrupt Cause Extension Descriptor|
|6040||4||Processor number of the processor currently executing in the kernel|
|8000||40||MCP Kernel Request Data (see KER instruction)|
There are 7 index registers available for use by application code. Typically used for address indexing (e.g. pointer following), three of the registers are mapped to low memory addresses (see table above) and the remaining four registers, known as mobile index registers because they are stored internally by the processor and are not mapped to memory locations, may only be altered with the LIX and SIX instructions.
An index register is an eight digit field using the SN data representation:
+=============================================+ | Sign | Base | 6 digit offset from base | +=============================================+ 0 1 2 3 4 5 6 7
The sign is as described above for the SN data representation. The Base digit, more formally known as the Base Indicant is used to select the memory area for a memory access. The use of Base digit values higher than 7 will lead to an Address Error fault. The offset field contains a value from zero to 999999 which will be summed with the operand address and the selected memory area base address to generate the absolute address of the memory location being accessed.
The NTR, VEN, RET and EXT (deprecated) use index register 3 (IX3) as a frame pointer that can be used to locate the previous value of IX3 after a VEN or NTR instruction. See the RET instruction for descriptions of the various stack frames.
An application executes in the context of a processor task. A processor task is represented to the hardware by an entry in the Reinstate List. When a task is not executing on a processor, the index registers for the task are stored in the associated reinstate list entry along with all other per-task processor state. The BRV instruction is used by the operating system kernel to context-switch to a new task on a processor.
The application memory model is a segmented model consisting of one or more environments each of which can address eight memory areas. Each memory area may consist of between 1,000 and 1,000,000 digit (500 to 500,000 bytes) addressable locations. Memory area zero, known as the data page, contains the per-application versions of the above reserved fields and is generally shared across all environments in an application since it provides the call-stack required for inter-environment function calls. The code for each environment is stored in memory area one. The remaining six memory areas are used for application data storage. While an environment is active, absolute base and limit addresses for each of the memory areas present in the environment are stored in internal processor registers. All instruction operands are relative to one of the active memory areas, with the memory area selected either implicitly (i.e. branch instruction targets are implicitly in memory area one) or explicitly via a base indicant digit in one of the index registers when the index register is used with operand addressing. The base indicant digit is the digit immediately following the sign digit and must be a value less than 8. The base indicant (sometimes known as a dimension override) is used to select the memory area base address to which the remaining six digits in the index register and the operand itself will be summed to obtain the absolute memory in address of the operand. Attempts to address outside the bounds of a memory area will result in an Address Error fault.
This is an example Task #2 memory layout: . The application has two code segments, each up to 500,000 bytes in size and two data segments both of which may reach up to 500,000 bytes in size. The data segments are accessible to both code segments.