Table of Contents

Interrupt Procedure

The interrupt procedure is executed whenever a processor has to enter the KERNEL mode to execute the MCP Kernel code. Since KERNEL mode is restricted to one processor only at any given time, the processor mode transitions are strictly controlled by a KERNEL MODE ACCESS LOCK. A processor requesting the KERNEL MODE ACCESS LOCK may be in either STOPPED, IDLE or EXECUTING mode.

The Interrupt Procedure is composed of three phases which are:

  1. The State Saving phase
  2. The Interrupting phase
  3. The Kernel Entry phase

The operations performed during the State Saving phase depend on the mode the processor is leaving.

To each phase is associated a time which is accounted differently. The way the State Saving phase time is charged depends upon the mode the processor is leaving:

The Interrupting phase is charged to the Interrupting time, and the Kernel Entry phase is charged to the Kernel time.

The User Task time is recorded via the Time Slice Remaining field in the reinstate list entry for that task. The Interrupting time and Kernel time are recorded and saved on a processor basis within the processor itself.

State Saving Phase

Processor is currently in EXECUTING mode

  1. The current Interrupt Mask is saved within the processor - it will be part of the interrupt frame. The new Interrupt Mask value is set to 00 - no additional maskable interrupts accepted.
  2. The Interrupt Descriptor which describes what interrupt(s) is active, is assembled and saved within the processor for future use. See Compatibility Notes A.60. The External Interrupt descriptor and the Instruction Interrupt Cause descriptor are also assembled and saved if needed. If the state saving is caused by an instruction related interrupt, the State Indicator field in the active Reinstate List Entry is updated. See Compatibility Notes A.46.
  3. The State of the interrupted task is assembled and written into the Interrupt Frame field of the active reinstate list entry. See Compatibility Notes A.46.
  4. The current task reinstate list pointer is assembled and saved within the processor for future use. Its format is C7AAAAAA where C is a positive sign, 7 is a Base Indicant, and AAAAAA is the absolute address of the active task reinstate list pointer.
  5. The current value of the task timer is stored into the Time Slice Remaining field of the active reinstate list entry. The value of the task timer is set to its maximum value.
  6. The processor is ready to leave the State Saving phase and enter Interrupting Phase

Processor is currently in IDLE mode

  1. The current Interrupt Mask is saved within the processor. The new Interrupt Mask value is set to 00 - no additional maskable interrupts accepted.
  2. The Interrupt Descriptor which describes what interrupt(s) is active, is assembled and saved within the processor for future use. See Compatibility Notes A.60. The External Interrupt descriptor is also saved, if needed.
  3. The value C7EEEEEE is saved within the processor for future update of the current task reinstate list pointer field in the Kernel Data Area.
  4. The current value of the task timer is used to compute the elapsed time spent in IDLE mode. This time is saved within the processor for future use. The value of the task timer is set to its maximum value.
  5. The processor is ready to leave the State Saving phase and enter the Interrupting phase.

Processor is currently in STOPPED mode

  1. The current Interrupt Mask is saved within the processor. The new Interrupt Mask value is set to 00 - no additional maskable interrupts accepted.
  2. The External Interrupt bit is set in the Interrupt Descriptor which is saved within the processor for future use. See Compatibility Notes A.60. The IPC bit i set in the External Interrupt Descriptor which is saved within the processor for future use.
  3. The value C7EEEEEE is saved within the processor for future update of the Current Task Reinstate list pointer in the Kernel Data Area.
  4. The processor is ready to leave the State Saving phase and enter the Interrupting phase.

Interrupting Phase

The Interrupting phase is the one during which the processor that is leaving its current mode (EXECUTING, IDLE or STOPPED), tries to obtain access to KERNEL mode by vying for the KERNEL MODE ACCESS LOCK. The following operations are performed during this phase:

  1. Set the processor mode to INTERRUPTING and try to obtain the KERNEL MODE ACCESS LOCK. See Compatibility Notes A.59.
  2. Once the lock is obtained, make sure that no other processor can obtain it until it is released by this processor.
  3. The current value of the task timer is used to compute the elapsed time spent in INTERRUPTING mode. This time is saved within the processor for future use. The value of the task timer is set to its maximum value.
  4. The processor is ready to leave the Interrupting phase and enter the Kernel Entry phase.

Kernel Entry Phase

The Kernel Entry phase is used to set up the initial state for the processor to begin executing instructions in the MCP's kernel.

  1. Set the processor mode to KERNEL
  2. If the processor is coming from EXECUTING mode, the Processor Number field of the active reinstate list entry is set to a value of 00.
  3. Update the Interrupting time for this processor by adding the value saved during the Interrupting phase to the previously recorded interrupting time for this processor. If the processor is coming from IDLE mode, update the Idle time for this processor by adding the value saved during the State Saving phase to the previously recorded idle time for the processor.
  4. The MOPOK line is set to zero while the measurement register is being changed and set to one at all other times.
  5. Update the current task reinstate list pointer field in the Kernel Data Area with the value that was saved within the processor.
  6. Update the Interrupt descriptor field in the Kernel Data Area with the value that was saved within the processor. If necessary, update the Instruction Interrupt Cause descriptor, the Instruction Interrupt Cause Extension descriptor and the External Interrupt Cause descriptor fields in the [processor_state:kernel_data_area|Kernel Data Area]] with the values saved within the processor.
  7. Update the Processor Number field in the kernel data area with the number value of the processor entering the kernel.
  8. If the interrupt was caused by the KER instruction, and Kernel Request data was specified, updat ethe kernel request data field in kernel data area with the information that was saved within the processor.
  9. Perform the Load Memory Area Table procedure using Task #1 Environment #0 as input parameters. See Compatibility Notes A.61.
  10. Set the next instruction address to the contents of the 6 digit Kernel Interrupt Branch Address field of the Kernel Data Area. The next instruction address is relative to the newly loaded Base #1.
  11. If any Hardware Call conditions exist for this processor, cause the processor to halt after storing the relevent Fault Indicators in the R/D Storage Area field in the Kernel Data Area.