Table of Contents

System and Processor Timers

A V Series system contains several system timers and processor timers. An entire system contains only one of each type of system timer. In contrast, each processor contains its own set of processor timers.

The System Timers are:

  1. Time of Day Timer
  2. Alarm Timer

Each processor contains the following additional processor timers:

  1. KERNEL mode timer
  2. INTERRUPTING mode timer
  3. IDLE mode timer
  4. Task Timer

Time of Day Timer

The Time of Day timer is a twenty digit counter that counts up at a one microsecond rate. See Compatibility Notes A.36.

The Time of Day Timer has the following format:

INFORMATION DIGITS
Year 00 - 03
Month 04 - 05
Day 06 - 07
Reserved 08
Microseconds 09 - 19

The Time of Day timer is set via the STT instruction. It may be read by any use that requires the time of day via the RDT instruction.

At midnight, sofwtare will initialize the day, month, year and microseconds via the STT instruction.

Alarm Timer

The Alarm Timer is a system timer which will cause an Alarm Timer interrupt to be reported to the system whenever the Microseconds field of the Time of Day timer is equal to or greater than the Microseconds field of the Alarm Timer. See Compatibility Notes A.59 for a description of when the various systems detect the Alarm Timer interrupt condition.

Processor Mode Timers

Each processor accumulates the time it spends in KERNEL mode, INTERRUPTING mode, and IDLE mode in the KERNEL mode timer, INTERRUPTING mode timer and the IDLE mode timer respectively.

These processor timers are stored in memory and cleared via the RDT instruction.

Task Timer

The Task Timer is a counter that is used to interrupt a task when its time splice has ended. The maximum timer value is about 900 seconds. The most significant digits of the timer controls the timer interrupt. The task timer will not be decremented when the processor is in INTERRUPTING mode.

If the Timer Interrupt bit is set in the Interrupt Mask, an Interrupt Procedure occurs that stores the adress of the next instruction to be executed whever the most significant digit of the timer is equal to zero.

If the Timer Interrupt bit is not set in the Interrupt Mask, the timer will continue to decrement at the same rate until an Interrupt Procedure is executed for any reason.

If an Interrupt has not occurred before the entire task timer reaches zero, a task timer fault will occur, which will cause a Hardware Call that will store the address of the next instruction to be executed. See Compatibility Notes A.45.

The Task Timer is affected by the Virtual Branch Reinstate instruction and the Interrupt Procedure.

The resolution of the Task Timer is machine dependent. See Compatibility Notes A.36.