Medium Systems/V-Series Architecture

General Description

This architecture consists of a powerful, high level variable length Instructions with up to three operand addresses each. It has instructions for data manipulation and local program control as well as more complex instructions to address outside of the local program environment and switch program environments. This family of instructions will also permit the system to address memory of greater than five million bytes. Addressing limitations are machine dependent. See Compatibility Notes A.53.

Operands may be fixed in length, may vary from 1 to 100 units, or may have their lengths defined by a begin/end address pair. In addition, data types may specify unsigned numeric, signed numeric, or unsigned data.

Fundamental Data Types

The system addresses memory to the four-bit digit. Digit representation:

Digit Binary Representation
0 0000
1 0001
2 0010
3 0011
4 0100
5 0101
6 0110
7 0111
8 1000
9 1001

The remaining binary representations are hereafter termed undigits and are generally not legal when used in arithmetic operations but are valid in certain contexts. In this document, numeric constants containing undigits will be bounded by the commercial-at symbol as defined by the Burroughs Programming Language (BPL) syntax.

Undigit Binary Representation
A 1010
B 1011
C 1100
D 1101
E 1110
F 1111

The sentinel value @EEEEEE@ is used as an end-of-list marker for certain instructions (SLT).

Signed Numeric (SN) Data

Data is interpreted in units of 4 bits (one digit). The sign is interpreted as a separate and leading 4-bit unit. The 4-bit code is interpeted by the arithmetic units as positive for all 4-bit values other than 1101 (@D@) which is interpreted as negative.

When the result of an operation is signed, the sign-digit is stored as follows:

+ 1100 (@C@)
- 1101 (@D@)

When the sign digit is interpreted as a plus, it will compare as HIGH relative to a sign digit interpreted as minus.

Unsigned Numeric (UN) Data

Data is interpreted in units of 4 bits (one digit).

Unsigned Alphanumeric (UA) Data

Data is interpreted in units of 8 bits (one byte or one character).

The internal representation of alpha data is in the Extended Binary Coded Decimal Interchange Code (EBCDIC). See Compatibility Notes B.02.

Eight-bit data is considered unsigned except in the case of the Move Alpha (OP = 10), Move Numeric (OP = 11), and Edit (OP = 49) instructions. Additional details are given in the description of these instructions.

Alphanumeric comparisons are binary and thus the low-to-high collating sequence for EBCDIC is symbols-alphas-digits.

Indirect Address (IA) Data

Indirect address data provides a level of indirection when resolving an operand. The data is stored as either an five-digit BCD offset from a base register, or an 8-digit extended instruction operand form encoding (see Instruction Operand Encoding).

Floating Point Data (B2500/B3500 only)

The B2500 and B3500 processors are capable of performing floating point arithmetic. If floating point arithmetic is used, the numeric data consists, in order from lowest addressed digit to highest addressed digit, a digit designating the sign of the exponent, a two-digit exponent, a digit designating the sign of the mantissa, and a variable length one to 100-digit mantissa. The exponent range is thus -99 to +99, a very large range. The mantissa is always a whole number with the decimal point assumed to the right of the last digit. Examples:

Value Floating Point Data
+123 +00+123
-1.23 -02-123
+0.0057 -04+57
-9.786 x 10(-6) -09-9786
+3.75 x 10(+6) +04+375

Instruction Representation

Reserved or not specified bits, digits or characters must be zero and are reserved for future specification. Ignored bits, digits or characters are not examined and may be any value.

All fields are addressed most significant digit first, unless specifically noted otherwise.

All instructions must start at an even address or cause and Address Error Fault (AEX = 43).

The data fields are called the A-field, the B-field and the C-field. AF and BF generally refer to the lengths of A and B fields respectively. The address of each field is called the A Address, the B address and the *C address*. The data type of each field is generally defined by the first digit (controller bits) of the A, B and C addresses.

Instruction Format

The processor instructions may vary in length from 4 to 30 digits. An instruction may use a mixture of Extended Address and Non-extended Address formats. Extended format is specified by the second digit of each of the A, B and C address syllables. An extended address occupies 8 digits whereas a non-extended address occupies 6 digits of an instruction.


OP = operator code (two digits)
V  = variant digits
AFBF = A and B-field length variant
A, B, C = Addresses of respective data fields.

Non Extended Format


Non-extended direct addressing capability is from 0 through 99,999. In a branch instruction, the two address controller bits can be used to extend the address range to 299,998

Extended Format


Extended direct addressing capability is from 0 through 999,999.

An Extended Indicant is specified if the high two order bits of the second most significant digit of an address syllable are true. An Extended Indicant signifies that the next six digits contain the address and determines which index registers may be specified for this address.

Extended/Non-Extended Addressing Format

     NON-EXTENDED ADDRESS      | xx xx | 5  | 4  | 3  | 2  | 1  |
                                  |  |    |    |    |    |    |
        Index Indicant ------------  |    |    |    |    |    |
        Address Controller -----------    |    |    |    |    |
                                          |    |    |    |    |
        Address Ten Thousands ------------|    |    |    |    |
        Address Thousands-----------------|----|    |    |    |
        Address Hundreds------------------|----|----|    |    |
        Address Tens----------------------|----|----|----|    |
        Address Ones----------------------|----|----|----|----|
                                          |    |    |    |    |
                                          |    |    |    |    |
 EXTENDED ADDRESS   | xx xx |  X  | 6  | 5  | 4  | 3  | 2  | 1  |
                       |  |    |     |
  Index Indicant--------  |    |     |
  Address Controller-------    |     |
  Extended Indicant-------------     |
  Address Hundred Thousands----------|

Address Resolution

Pre-Omega Address Resolution (B3500 through B4900)

The decimal addressing technique used in core memory allows data to be addressed in variable length fields of 16-bit words, 8-bit (byte) or 4-bit (digit) units. Even though memory is addressable to a digit position, memory is accessed by means of a 2-byte word, plus a parity bit. Internally, the processor is capable of operating with any 8-bit code, two of which are programmatically selectable (EBCDIC and USASCII).

Omega Address Resolution (V3x0 through V5x0)

Under the MCP for the V Series machines, most of the MCP and all user programs are partitioned into a number of separate memory pieces. Each is defined by its base and limit which are always congruent to zero modulo 1000. All addresses to this memory are relative to one of those base and limits.

All processes running under the MCP on these machines have accessibility to memory via eight base and limit pairs. Base #0 is define as that process' context (data) area. Base #1 is defined as that process' code area. Non-indexed addresses will refer to base #0 or base #1, depending on whether the address refers to data or core respectively. In order to support user programs with only one base and limit 9i.e. with the intermixed code and data), both base #0 and base #1 point to the same area of memory.

Processes can also address memory via all 8 base and limit pairs through the use of the base indicant digit in one of the Index Registers. With non-extended addressing, IX1, IX2 and IX3 can be used. Extended addressing also allows the use of IX4, IX5, IX6 and IX7.

Addresses will be resolved according to the following chart:

Addressing Mode
None 0 Context Relative
None 1 IX1 w/Base Indicant
None 2 IX2 w/Base Indicant
None 3 IX3 w/Base Indicant
A 0 Address Error
A 1 Address Error
A 2 Address Error
A 3 Address Error
B 0 Address Error
B 1 Address Error
B 2 Address Error
B 3 Address Error
C 0 Context Relative
C 1 IX1 w/Base Indicant
C 2 IX2 w/Base Indicant
C 3 IX3 w/Base Indicant
D 0 Code Base Relative (Base #1)
D 1 IX4 w/Base Indicant
D 2 IX5 w/Base Indicant
D 3 IX6 w/Base Indicant
E 0 Address Error
E 1 IX7 w/Base Indicant
E 2 Address Error
E 3 Address Error
F 0 Address Error
F 1 Address Error
F 2 Address Error
F 3 Address Error

Non-Indirect Address

A non-indirect context relative address is relative to the Code Base (Base #1) for the following instruction opcodes:

OP Mnemonic Name
20 NOP No Operation
21 LSS Branch on Less
22 EQL Branch on Equal
23 LEQ Branch on Less Than or Equal
24 GTR Branch on Greater
25 NEQ Branch on Not Equal
26 GEQ Branch on Greater than or Equal
27 BUN Branch Unconditionally
28 OFL Overflow
29 HBR Halt Branch
2A NUL Branch on NULL
2B GTN Branch on Greater than or NULL
31 NTR Enter
32 EXT Exit

A non-indirect context relative address is relative to the Data Base (Base #0) for all other instruction opcodes.

Address digits are limited to the decimal values of 0-9. Undigits in a resolved final address will cause an Address Error fault.

Memory Organization

System memory is organized as a sequence of digits addressed starting with the address zero. An ABSOLUTE address ranges from six digits to nine digits in length, depending on the processor generation.

Processor Memory Address Size in digits
B3500 6
B4900, V3x0, V4x0 8
V5x0 9

ABSOLUTE addresses are only used by the Master Control Program (MCP) when setting up the addressing structures used to provide a virtual address space to application tasks.

Application Memory Organization

From the B3500 through the B4900 processors, a normal-state application was granted a single address space which started at zero and was limited to 1,000,000 digits. Two privileged registers were maintained by the processor that contained the ABSOLUTE addresses in units of 1000 digits of the base and limit of the region assigned to the current normal-state task. Control-state code in the MCP would allocate a contiguous region of memory to the task and load the base-limit registers with the Branch Reinstate (BRE) instruction.

Sub-BASE memory

The B4900, V3x0 and V4x0 processor families reserve the first 10 pages (10,000 digits) of system memory for the processor to use. This memory is generally invisible to the MCP, but the MCP must include it when storing ABSOLUTE addresses in system registers (e.g. Write Hardware Register (WHR)) and base/limit registers on machines in this family.

Pre-Omega Sub BASE Address Function
00380 - 00389 Snap Picture Report Address (Contains an ABSOLUTE BASE relative address of the form: 000AAAAAAA)
00390 - 00399 Memory Error Report Address (Contains an MCP BASE relative address of the form: 000aaaaaaa)
00400 - 03999 I/O Memory Scratchpad (400 + (channel * 32))
00400 - 00407 Channel 00 Current Buffer Address
00408 - 00415 Channel 00 Buffer End Address
00416 - 00423 Channel 00 Extended Result Descriptor (R/D)
00424 - 00427 Channel 00 Accumulated R/D (IOP use only)
00428 Channel 00 Busy Flag
00429 - 00431 Channel 00 unused
00432 - 00439 Channel 01 Current Buffer Address
00656 - 00657 Channel 08 (IOP channel) Channel number for IIO
00658 - 00663 Channel 08 (IOP channel) I/O Descriptor Command
00664 - 00671 Channel 08 (IOP channel) A address
00672 - 00679 Channel 08 (IOP channel) B address
00680 - 00687 Channel 08 (IOP channel) C address
02864 - 02871 Channel 77 Current Buffer Address
02872 - 02879 Channel 77 Buffer End Address
02880 - 02887 Channel 77 Extended Result Descriptor (R/D)
02888 - 02891 Channel 77 Accumulated R/D (IOP use only)
02892 Channel 77 Busy Flag
02893 - 02895 Channel 77 unused

The 32-digit entry for channel 8 (The I/O Processor (IOP) channel) is used for the mailbox interface between the IOP and the Execute Modules (XM's) when processing the Initiate I/O (IIO) instruction. If the first two digits of the I/O descriptor are not in the 60-69 range, then the C address (generally sector number for disk I/Os) is left justified into the C address mailbox field with two trailing zeros.

Omega Sub BASE Address Function
00220 - 00229 Memory Area Status Table (MAST) Base address (see Write Hardware Register (WHR))
00230 - 00239 Unused
00240 - 00249 Reinstate List Base Address (Hardware Address) (see Write Hardware Register (WHR))
00250 - 00269 Unused
00270 - 00279 Number of entries in the MCP Environment Table (6 digits, right justified)
00280 - 00289 Number of entries in the User Environment Table (6 digits, right justified)
00290 - 00299 Reinstate List Current Entry Address (Hardware Address) (see Branch Reinstate Virtual (BRV))
00300 - 00307 Mobile IX4
00308 - 00315 Mobile IX5
00316 - 00323 Mobile IX6
00324 - 00331 Mobile IX7
00332 - 00339 Unused
00340 - 00340 Time of Day Timer (Part I - YYYYMMDD00)
00350 - 00359 Time of Day Timer (Part II - SSSSSSSS00)
00360 - 00369 Task Timer for Current Task (TTTTTT0000)
00370 - 00370 Memory Error Report Pending (Written)
00371 - 00379 Unused
00380 - 00389 Snap Picture Report Address (Machine Base)
00390 - 00399 Memory Error Report Address (Contains an MCP BASE relative address of the form: 000aaaaaaa)
00400 - 00655 IOP Scratchpad
00656 - 00688 IOP Mailbox (Part of IP Scratchpad)
00689 - 03999 IOP Scratchpad
04000 - 09999 Unused

Pre-Omega ABSOLUTE BASE memory

Certain ABSOLUTE BASE relative addresses within the first thousand digits (colloquially, page) of memory are reserved for special functions.

ABSOLUTE BASE relative address Function
00 - 38 Indirect Field Lengths (see Indirect Field Length)
08 - 15 MCP Index Register 1
16 - 23 MCP Index Register 2
24 - 32 MCP Index Register 3 (Frame Pointer)
38 SCAN Location (see Scan Delimiter Equal (SDE), SDU, SZE, SZU)
40 - 45 MCP top of Stack (TOS) address
46 - 47 Halt Mask (see Halt Breakpoint (HBK))
48 Halt Digit (see Halt Digit, Halt Branch (HBR))
60 - 76 Run Control Word (see Branch Reinstate (BRE))
80 - 83 Processor Control Word
84 - 93
94 - 99 BCT 94 target address (interrupt vector)
100-103 Channel 0 Result Descriptor word one
104-107 Channel 0 Link to next R/D
108-113 Software Usage
114-119 BCT 114 handler address.
120-133 Channel 1 Result Descriptor and Link
134-139 BCT 134 handler address.
140-159 Channel 2 Result Descriptor and Link
240-259 Channel 7 Result Descriptor and Link
260-279 Channel 8 IOT Result Descriptor and Link
300-319 Channel 10 Result Descriptor and Link
500-619 Channel 20 Result Descriptor and Link
B3500: Multiline Adapter 01 Result Descriptor and Link
700-819 Channel 30 Result Descriptor and Link
900-1019 Channel 40 Result Descriptor and Link
1100-1119 Channel 50 Result Descriptor and Link
1300-1319 Channel 60 Result Descriptor and Link
1500-1519 Channel 70 Result Descriptor and Link
1640-1659 Channel 77 Result Descriptor and Link

In 1979, development started of the Omega Architecture to extend the addressing capabilities of the medium systems line while maintaining compatibility with existing compiled applications. This architecture increased both the amount of total memory that could be installed on a system as well as the amount of total memory that could be used by a single application task.

Omega Memory Architecture

Omega added a set of data structures that the MCP could use to describe the application address space. For compatibility with existing object code, a single segment continued to be restricted to a million digits or less in size, but an application could have up to eight segments accessible simultaneously in a single Environment (allowing access to up to eight million digits) and could have up to 1,000,000 of these Environments accessible via function calls. The architecture also allowed the MCP to address up to 99,999 environments.

Reinstate List

The Reinstate List is a hardware data structure that contains the address of the Environment Table which describes the addressing environment for the task. The brv instruction is used by the MCP kernel specify the active reinstate list entry on each processor.

architecture.txt · Last modified: 2019/08/10 14:24 by scott
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