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architecture [2018/02/27 07:58]
scott [Fundamental Data Types]
architecture [2018/03/17 15:30] (current)
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 ====== Medium Systems/V-Series Architecture ====== ====== Medium Systems/V-Series Architecture ======
 +
 +===== General Description =====
 +
 +This architecture consists of a powerful, high level variable length
 +instrutions of up to three operand addresses each.  It has instructions for
 +data manipulation and local program control as well as more complex
 +instructions to address outside of the local program environment and switch
 +program environments.  This family of instructions will also permit hte system
 +to address memory of greater than five million bytes.   Addressing limitations
 +are machine dependent.   See [[compatibility_notes:a53|Compatibility Notes A.53]].
 +
 +[[instruction:operand_format:Operands]] may be fixed in length, may vary from 1 to 100 units, or may have
 +their lengths defined by a begin/end address pair.   In addition, data types
 +may specify unsigned numeric, signed numeric, or unsigned data.
  
 ===== Fundamental Data Types ===== ===== Fundamental Data Types =====
Line 17: Line 31:
 |  9 |  1001  | |  9 |  1001  |
  
-The remaining binary representations are termed **undigits** and are generally not legal when used in arithmetic operations but are valid in certain contexts.+The remaining binary representations are hereafter termed **undigits** and are generally not legal when used in arithmetic operations but are valid in certain contexts.
 In this document, numeric constants containing undigits will be bounded by the commercial-at symbol as defined by the [[language:bpl|Burroughs Programming Language (BPL)]] syntax. In this document, numeric constants containing undigits will be bounded by the commercial-at symbol as defined by the [[language:bpl|Burroughs Programming Language (BPL)]] syntax.
  
-Digit  ^ Binary Representation  ^+Undigit  ^ Binary Representation  ^
 |  A |  1010  | |  A |  1010  |
 |  B |  1011  | |  B |  1011  |
Line 30: Line 44:
 The sentinel value @EEEEEE@ is used as an end-of-list marker for certain instructions ([[instructions:slt|SLT]]). The sentinel value @EEEEEE@ is used as an end-of-list marker for certain instructions ([[instructions:slt|SLT]]).
  
-=== Unsigned Numeric (UN) Data ===+=== Signed Numeric (SN) Data ===
  
-An unsigned numeric data item is a sequence of digits in memory from one to 100 digits in length.   The most significant digit is stored as the first digit of the data item in memory followed by digits of lesser significance.+Data is interpreted in units of 4 bits (one digit).   The sign is interpreted 
 +as a separate and leading 4-bit unit.  The 4-bit code is interpeted by the 
 +arithmetic units as positive for all 4-bit values other than 1101 (@D@) which 
 +is interpreted as negative.
  
-=== Signed Numeric (SN) Data ===+When the result of an operation is signed, the sign-digit is stored as 
 +follows: 
 + 
 +^ + | 1100 (@C@)  | 
 +^ - | 1101 (@D@)  | 
 + 
 +When the sign digit is interpreted as a //plus//, it will 
 +[[processor_state:comparison_flags|compare as HIGH]] relative to a sign digit 
 +interpreted as //minus//. 
 + 
 +=== Unsigned Numeric (UN) Data ===
  
-A signed numeric data item is a sequence of digits in memory from one to 100 digits in length.   The first digit represents the sign of the data item.  The processor interprets any digit value other than @D@ as a positive sign, and @D@ as a negative sign.   The processor will normalize the positive sign to @C@ when storing a signed numeric data item in memory.+Data is interpreted in units of 4 bits (one digit).
  
 === Unsigned Alphanumeric (UA) Data === === Unsigned Alphanumeric (UA) Data ===
  
-An unsigned alphanumeric data item is a sequence of between one and 100 two-digit (one byte) data items stored consecutively in memory.  When interpreted by the processor, the bytes are interpreted using the Extended Binary-Coded Decimal Interchange Code (**EBCDIC**).     Arithmetic operations are valid on UA data - the processor will ignore the zone (high-orderdigit for UA arithmetic input operands and will normalize the **EBCDIC** zone digit to the digit **@F@** for UA output operands (see [[compatibility_notes:b00|Compatibility Note]]).    When one or more of the input operands is SN and the output operand is UA, the sign will be encoded in the low-order digit of the first byte of the UA operand, otherwise UA operands are considered to be unsigned.+Data is interpreted in units of 8 bits (one byte or one character)
 + 
 +The internal representation of alpha data is in the Extended Binary Coded 
 +Decimal Interchange Code (**EBCDIC**).  See [[compatibility_notes:b02|Compatibility Notes B.02]]. 
 + 
 +Eight-bit data is considered unsigned except in the case of the [[instructions:mva|Move Alpha (OP = 10)]], [[instructions:mvn|Move Numeric (OP = 11)]], and [[instructions:edt|Edit (OP = 49)]] instructions Additional details are given in the description of these instructions. 
 + 
 +Alphanumeric comparisons are binary and thus the low-to-high collating 
 +sequence for **EBCDIC** is symbols-alphas-digits.
  
 === Indirect Address (IA) Data === === Indirect Address (IA) Data ===
  
 Indirect address data provides a level of indirection when resolving an operand.   The data is stored as either an five-digit BCD offset from a base register, or an 8-digit extended instruction operand form encoding (see [[instruction:operand_encoding|Instruction Operand Encoding]]). Indirect address data provides a level of indirection when resolving an operand.   The data is stored as either an five-digit BCD offset from a base register, or an 8-digit extended instruction operand form encoding (see [[instruction:operand_encoding|Instruction Operand Encoding]]).
 +
 +===== Instruction Representation =====
 +
 +//Reserved// or //not specified// bits, digits or characters must be zero
 +and are reserved for future specification.  Ignored bits, digits or characters
 +are not examined and may be any value.
 +
 +All fields are addressed most significant digit first, unless specifically
 +noted otherwise.
 +
 +All instructions must start at an even address or cause and Address Error
 +Fault (AEX = 43).
 +
 +The data fields are called the //A-field//, the //B-field// and the //C-field//.  **AF** and
 +**BF** generally refer to the lengths of A and B fields respectively.  The address
 +of each field is called the **A Address**, the **B address** and the *C address*.  The
 +data type of each field is generally defined by the first digit (controller
 +bits) of the A, B and C addresses.
 +
 +==== Instruction Format ====
 +
 +The processor instructions may vary in length from 4 to 30 digits.  An
 +instruction may use a mixture of Extended Address and Non-extended Address
 +formats.  Extended format is specified by the second digit of each of the A, B
 +and C address syllables.   An extended address occupies 8 digits whereas a
 +non-extended address occupies 6 digits of an instruction.
 +
 +Key:
 +
 +  OP = operator code (two digits)
 +  V  = variant digits
 +  AFBF = A and B-field length variant
 +  A, B, C = Addresses of respective data fields.
 +
 +=== Non Extended Format ===
 +
 +  OP VV
 +  OP VVVV
 +  OP AAAA
 +  OP AAAAAA
 +  OP AFBF AAAAAA
 +  OP AFBF AAAAAA BBBBBB
 +  OP AFBF AAAAAA BBBBBB CCCCCC
 +
 +Non-extended direct addressing capability is from 0 through 99,999.  In a
 +branch instruction, the two address controller bits can be used to extend the
 +address range to 299,998
 +
 +=== Extended Format ===
 +
 +  OP AAAAAAAA
 +  OP AFBF AAAAAAAA
 +  OP AFBF AAAAAAAA BBBBBBBB
 +  OP AFBF AAAAAAAA BBBBBBBB CCCCCCCC
 +
 +Extended direct addressing capability is from 0 through 999,999.
 +
 +An Extended Indicant is specified if the high two order bits of the second
 +most significant digit of an address syllable are true.  An Extended Indicant
 +signifies that the next six digits contain the address and determines which
 +[[processor_state:index_registers|index registers]] may be specified for this address.
 +
 +=== Extended/Non-Extended Addressing Format ===
 +
 +                                 +-------+----+----+----+----+----+
 +       NON-EXTENDED ADDRESS      | xx xx | 5  | 4  | 3  | 2  | 1  |
 +                                 +-------+----+----+----+----+----+
 +                                    |  |    |    |    |    |    |
 +          Index Indicant ------------  |    |    |    |    |    |
 +          Address Controller -----------    |    |    |    |    |
 +                                            |    |    |    |    |
 +          Address Ten Thousands ------------|    |    |    |    |
 +          Address Thousands-----------------|----|    |    |    |
 +          Address Hundreds------------------|----|----|    |    |
 +          Address Tens----------------------|----|----|----|    |
 +          Address Ones----------------------|----|----|----|----|
 +                                            |    |    |    |    |
 +                                            |    |    |    |    |
 +                      +-------+----------+----+----+----+----+----+
 +   EXTENDED ADDRESS   | xx xx |  X  | 6  | 5  | 4  | 3  | 2  | 1  |
 +                      +-------+----------+----+----+----+----+----+
 +                         |  |    |     |
 +    Index Indicant--------  |    |     |
 +    Address Controller-------    |     |
 +    Extended Indicant-------------     |
 +    Address Hundred Thousands----------|
 +
 +===== Address Resolution =====
 +
 +==== Pre-Omega Address Resolution (B3500 through B4900) ====
 +
 +==== Omega Address Resolution (V3x0 through V5x0) ====
 +
 +Under the MCP for the V Series machines, most of the MCP and all user programs
 +are partitioned into a number of separate memory pieces.   Each is defined by
 +its bas and limit which are always MOD 1000.   All addresses to this memory
 +are relative to one of those base and limits.
 +
 +All processes running under the MCP on these machines have accessability to
 +memory via eight base and limit pairs.   Base #0 is define as that process'
 +context (data) area.   Base #1 is defined as that process' code area.
 +Non-indexed addresses will refer to base #0 or base #1, depending on whether
 +the address refers to data or core respectively.   In order to support user
 +programs with only one base and limit 9i.e. with the intermixed code and
 +data), both base #0 and base #1 point to the same area of memory.
 +
 +Processes can also address memory via all 8 base and limit pairs through the
 +use of the **base indicant** digit in one of the
 +[[processor_state:index_registers|Index Registers]].  With non-extended
 +addressing, IX1, IX2 and IX3 can be used.    Extended addressing also allows
 +the use of IX4, IX5, IX6 and IX7.
 +
 +Addresses will be resolved according to the following chart:
 +
 +^ Extended\\ Indicant  ^ Index\\ Indicant  ^ Addressing Mode ^
 +|  None  |  0  | Context Relative  |
 +|  None  |  1  | IX1 w/Base Indicant  |
 +|  None  |  2  | IX2 w/Base Indicant  |
 +|  None  |  3  | IX3 w/Base Indicant  |
 +|  A  |  0  | Address Error  |
 +|  A  |  1  | Address Error  |
 +|  A  |  2  | Address Error  |
 +|  A  |  3  | Address Error  |
 +|  B  |  0  | Address Error  |
 +|  B  |  1  | Address Error  |
 +|  B  |  2  | Address Error  |
 +|  B  |  3  | Address Error  |
 +|  C  |  0  | Context Relative  |
 +|  C  |  1  | IX1 w/Base Indicant  |
 +|  C  |  2  | IX2 w/Base Indicant  |
 +|  C  |  3  | IX3 w/Base Indicant  |
 +|  D  |  0  | Code Base Relative (Base #1)  |
 +|  D  |  1  | IX4 w/Base Indicant  |
 +|  D  |  2  | IX5 w/Base Indicant  |
 +|  D  |  3  | IX6 w/Base Indicant  |
 +|  E  |  0  | Address Error  |
 +|  E  |  1  | IX7 w/Base Indicant  |
 +|  E  |  2  | Address Error  |
 +|  E  |  3  | Address Error  |
 +|  F  |  0  | Address Error  |
 +|  F  |  1  | Address Error  |
 +|  F  |  2  | Address Error  |
 +|  F  |  3  | Address Error  |
 +
 +=== Non-Indirect Address ===
 +
 +A non-indirect context relative address is relative to the Code Base (Base #1)
 +for the following instruction opcodes:
 +
 +^ OP  ^ Mnemonic  ^ Name  ^
 +| 20  | [[instructions:nop|NOP]]  | No Operation  |
 +| 21  | [[instructions:lss|LSS]]  | Branch on Less  |
 +| 22  | [[instructions:eql|EQL]]  | Branch on Equal  |
 +| 23  | [[instructions:leq|LEQ]]  | Branch on Less Than or Equal  |
 +| 24  | [[instructions:gtr|GTR]]  | Branch on Greater  |
 +| 25  | [[instructions:neq|NEQ]]  | Branch on Not Equal  |
 +| 26  | [[instructions:geq|GEQ]]  | Branch on Greater than or Equal  |
 +| 27  | [[instructions:bun|BUN]]  | Branch Unconditionally  |
 +| 28  | [[instructions:ofl|OFL]]  | Overflow  |
 +| 29  | [[instructions:hbr|HBR]]  | Halt Branch  |
 +| 2A  | [[instructions:nul|NUL]]  | Branch on NULL  |
 +| 2B  | [[instructions:gtn|GTN]]  | Branch on Greater than or NULL  |
 +| 31  | [[instructions:ntr|NTR]]  | Enter  |
 +| 32  | [[instructions:ext|EXT]]  | Exit  |
 +
 +A non-indirect context relative address is relative to the Data Base (Base #0)
 +for all other instruction opcodes.
 +
 +Address digits are limited to the decimal values of 0-9.  Undigits in a
 +resolved final address will cause an //Address Error// fault.
  
 ===== Memory Organization ===== ===== Memory Organization =====
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 |  48  | Halt Digit (see [[processor_state:halt_digit|Halt Digit]], [[instructions::hbr|Halt Branch (HBR)]])  | |  48  | Halt Digit (see [[processor_state:halt_digit|Halt Digit]], [[instructions::hbr|Halt Branch (HBR)]])  |
 |  60 - 76  | Run Control Word (see [[instructions:BRE|Branch Reinstate (BRE)]])  | |  60 - 76  | Run Control Word (see [[instructions:BRE|Branch Reinstate (BRE)]])  |
 +|  80 - 83  | [[processor_state:processor_control_word|Processor Control Word]]  |
 +|  84 - 93  |     |
 +|  94 - 99  | [[instructions:bct|BCT]] 94 target address (interrupt vector)  |
 +|  100-103  | Channel 0 [[result_descriptor|Result Descriptor]] word one  |
 +|  104-107  | Channel 0 [[instructions:srd|Link to next R/D]]  |
 +|  108-113  | Software Usage  |
 +|  114-119  | BCT 114 handler address.  |
 +|    ...    |  ...   |
 +|  120-133  | Channel 1 [[result_descriptor|Result Descriptor]] and Link  |
 +|  134-139  | BCT 134 handler address.  |
 +|    ...    |  ...   |
 +|  140-159  | Channel 2 [[result_descriptor|Result Descriptor]] and Link  |
 +|    ...    |  ...   |
 +|  240-259  | Channel 7 [[result_descriptor|Result Descriptor]] and Link  |
 +|    ...    |  ...   |
 +|  260-279  | Channel 8 [[iot_result_descriptor|IOT Result Descriptor]] and Link  |
 +|  280-299  |    |
 +|  300-319  | Channel 10 [[result_descriptor|Result Descriptor]] and Link  |
 +|    ...    |  ...   |
 +|  500-619  | Channel 20 [[result_descriptor|Result Descriptor]] and Link  |
 +|    :::    | B3500: Multiline Adapter 01 [[result_descriptor|Result Descriptor]] and Link  |
 +|    ...    |  ...   |
 +|  700-819  | Channel 30 [[result_descriptor|Result Descriptor]] and Link  |
 +|    ...    |  ...   |
 +|  900-1019  | Channel 40 [[result_descriptor|Result Descriptor]] and Link  |
 +|    ...    |  ...   |
 +|  1100-1119  | Channel 50 [[result_descriptor|Result Descriptor]] and Link  |
 +|    ...    |  ...   |
 +|  1300-1319  | Channel 60 [[result_descriptor|Result Descriptor]] and Link  |
 +|    ...    |  ...   |
 +|  1500-1519  | Channel 70 [[result_descriptor|Result Descriptor]] and Link  |
 +|    ...    |  ...   |
 +|  1640-1659  | Channel 77 [[result_descriptor|Result Descriptor]] and Link  |
  
 In 1979, development started of the **Omega Architecture** to extend the addressing capabilities of the medium systems line while maintaining compatibility with existing compiled applications.  This architecture increased both the amount of total memory that could be installed on a system as well as the amount of total memory that could be used by a single application task. In 1979, development started of the **Omega Architecture** to extend the addressing capabilities of the medium systems line while maintaining compatibility with existing compiled applications.  This architecture increased both the amount of total memory that could be installed on a system as well as the amount of total memory that could be used by a single application task.
architecture.1519747121.txt.gz · Last modified: 2018/02/27 07:58 by scott
 
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