Cabinet Configurations

B3500 (2-cabinet configuration):

  • 1 processor
  • 1 Central Control/Memory Base (10KB to 60KB), 3 large and 3 small I/O controls
  • 24 words address memory
  • 4 to 6 I/O channels
  • 1 to 6 I/O controls

B2500/B3500 (3-Cabinet configuration):

  • 1 Processor
  • 1 to 2 Central Control B cabinets (up to 10 I/O controls)
  • 1 to 4 Memory Module Base B cabinets (10KB to 500KB, max 3 cabinets; 150KB for first 2 cabinets, 200K for third)
  • 0 to 2 Aux cabinets (Contains exchanges and multiline extensions)
  • 24 to 120 words of Address Memory (8 extensions, each 12 words; multiline control with all multiline extensions requires 6 extensions)
  • 1 to 2 AC Power Supply cabinets (4-6 cabinets require 1, 7-9 cabinets require 2)
  • DC Power supply is modular depending on system demands. Installed in memory base B; not requires in Aux Cabinet.
  • 6 to 20 I/O channels
  • 1 to 20 (19 if Multiline control installed) I/O controls and exchanges

Cabinet Dimensions: 17.3 in wide, 60.5 in tall, 77.5 inches long.

There are five cabinets in the central system:

  • Processor
  • Central Control and Memory Base
  • Memory Base B
  • Central Control B
  • Auxiliary

A B2500 system consists of one processor cabinet, and one central control and memory base cabinet. The maximum length of the coaxial cable between these two cabinets is 35 feet (25 feet is standard). A B2501 supports up to six I/O channels. A B2502 supports up to eight I/O channels.

A B3500 system consists of one processor cabinet, at least one and ad most two Central Control B cabinets, and at least one and at most four Memory Base B cabinets. The maximum length of the coaxial cables between any two of these cabinets is 35 feet (25 feet is standard). Up to two Auxiliary cabinets may be added, as required.

Core Memory

The memory consists of a highly modular group of components to provide a variety of memory sizes for both the B2500 and B3500 systems. Each B2500 system may have memory sizes ranging from 10,000 bytes to 60,000 bytes in increments of 10,000 bytes. Each B3500 system may have memory sizes of from 10,000 bytes to 500,000 bytes in variable increments. The increments of the B3500 core memory are as follows:

From To Byte Increment(s)
10,000 90,000 10,000
90,000 240,000 30,000
240,000 360,000 60,000
360,000 450,000 90,000
450,000 500,000 50,000

Decimal addressing allows for addressing any single digit within core memory. Even though a digit position can be addressed, the memory access is made on the word in which the digit is located. A B2500 or B3500 word consists of two bytes and a parity bit (16 bits plus parity). Whenever a byte is addressed, the decimal address must be an even address. Whenever a 16-bit word is addressed, the decimal address must be congruent to zero modulo four. The memory cycle time for one word is one microsecond on the B3500. The B2500 has a word cycle time of two microseconds.

Address Memory

Address memory is a modular array of storage registers. Each register within the array consists of a six-digit word capable of containing an address. Each B2500 or B3500 system includes 24 words of address memory. Six words are used by the processor to store the three addresses and other logical requirements of an instruction. Two words contain real-time clock and control-time interval used by the software. The remaining 16 words are used in pairs by the input/output channels for I/O operations. A total of eight address memory extensions, each consisting of 12 words, can be added to a B3500 system. Therefore, address memory is modular from 24 to 120 words in increments of 12 words. The addition of input/output channels may require the addition of address memory extensions.

Central Control

The central Control essentially provides:

  1. Priority Resolution between I/O controls within central control
  2. Result Descriptor address generation for the I/O controls
  3. Interface from the processor used to initial I/O control activity
  4. A common bus shared by all I/O controls
  5. Interface to Address Memory in the processor to manipulate addresses.
  6. A standard interface to each control attached
  7. Provision for a BCL/EBCDIC translator.

I/O Control priority within a central control cabinet is changable. Central control requests access from the highest to the lowest priority one at a time, in turn.

Priority between central control cabinets is determined in the central processor. There are equal levels of priority between centeral control cabinets. Access is granted to the central control which was not granted the last access by the logic in the processor.

Access is granted to the processor if, and only if, no requests are made by central control.


A plug-in translator is provided optionally as a part of central control. The translator can provide BCL to EBCDIC translation of data as it is transferred from an input unit to main memory. The translation of EBCDIC to BCL can also be made on information being transferred from main memory to an output device. For each transfer through central control, a signal from the requesting I/O control indicates whethyer the data is to pass through or bypass the translator. Since the translation is accomplished by the hardware, there is no slowdown in the transfer process. All EBCDIC codes outside the graphic set are translated to the BCL code for a question mark. A substitution is made when there is no conflict, i.e. the BCL graphic is not contained in the EBCDIC graphic set and vice versa.


The processor contains the necessary logic and circuitry to execute all instructions. It can operate in any one of four states:

  1. Control State, zero base - The interrupt flip-flop can be set, but the interrupt branch is not executed until the return to normal state. Privileged instructions are allowed
  2. Control State, non-zero base - The interrupt flip-flop can be set, but the interrupt branch is not executed until the return to normal state. Privileged instructions are disallowed.
  3. Normal State, zero base - The interrupt branch is allowed to be executed and privileged instructions are allowed
  4. Normal State, non-zero base - The interrupt branch is allowed to be executed and privileged instructions are disallowed.

Note: Some error conditions which result in a processor result descriptor being stored will not set the interrupt flip-flop, but the interrupt branch is executed directly.

Object programs, assemblers, compilers, generators, etc., are executed in normal state, non-zero base whereas most of the Master Control Program is executed in the control state, zero base. A small set of privileged instructions (used exclusively by the Master Control Program) can only be executed in zero base. This includes such commands as Initiate I/O and Read Timer.

Automatic interrupt detection is an integral part of the processor whenever the processor is operating in normal state. When a result descriptor is generated and stored, an interrupt occurs after the current instruction is completed.

The processor is changed to operate in control state, zero base and an automatic branch is executed to the interrupt handling routine of the software after storing the return point and logical registers for program reentry. Result descriptors contain the information necessary to determine the type of interrupt that occurred.

Logical Units

Included in the processor are logical units that are used or changed by instructions. All instruction addresses, and the data field addresses within the instructions, are relative to a base register. The base registerr is added to all instruction addresses to create the absolute memory address of an instruction or data field. The base register value is set by the Master Control Program. There are also three index registers available to every program being operated. Thus, the absolute memory address can consist of the algebraic sum of the base register, the relative address and one of the three index registers. To ensure memory protection, a program also has a limit register that is set by the Master Control Program. All memory addresses are checked automatically to determine if the address is within the bounds of the base and limit address registers.

Other logical units utilized are the overflow flip-flop, the comparison flip-flops, the normal/control state flip-flop, the mode flip-flop and the interrupt flip-flop.

Processor Interrupts

Whenever the processor is operating in the non-zero base, any of the following conditions will generate a result descriptor and cause the interrupt branch to take place.

  1. A memory parity error during a memory access by the processor
  2. Detection of a memory address error
  3. Execution time of an instruction exceeds a preset adjustable limit
  4. Attempt to execute an invalid instruction such as
    • Non-assigned opcodes
    • Non-present options
    • Invalid halts
    • Invalid Communicate addresses (non-decimal digits)
    • Invalid Communicate address (first digit must be 1)
    • Privileged Instruction

An interrupt generated by the real-time clock sets the interrupt flip-flop.

The processor result descriptor contains the information necessary to determine the type of interrupt(s) that occurred. This enables the interrupt handling routine of the software to take the necessary steps to process the specific interrupt(s). If conditions 1, 2, or 3 or the first three bullets of condition 4 occur when operating in zero base, the processor clock is turned off and processing stops (colloquially known as a Red Light condition for the console indicator that illuminates in this situation). An additional interrupt that only occurs in zero base is the execution of an invalid I/O operation. This interupt and the clock interrupt generate a result descriptor and set the interrupt flip-flop. Automatic branching does not occur while operating in the control state.

Read-Only Memory

The read-only memory of the processor is a resistive type of storage. It contains a set of microprograms that controls most of the actions taken by the processor. The microprograms are initiated by the operation codes of program instructions after they are fetched from memory. The microprograms utilize the addresses stored in address memory during execution of the instruction.

During the fetch cycle of an instruction, the absolute addresses are assembled and stored in address memory. The use of read-only memory and address memory reduces tyhe number of “hard registers” within B2500 and B3500 systems.

Input/Output System

The input/output system of the B2500 or B3500 consists of the input/output channels and the input/output or peripheral controls/exchanges. All of the input/output operations are initiated, but are not executed by the processor. The execution of any specific input/output operation is accomplished by an I/O control unit. The I/O operation may be executed simultaneously with a processor operation and other previously initiated I/O operations on other I/O channels. The type of input/output operation is determined by an I/O Descriptor that is transferred to the input/output control by an Initiate I/O operation of the processor. At the conclusion of an I/O operation, a Result Descriptor is generated and stored, and the interrupt flip-flop is set ON. The result descriptor will specify any exception that may have occurred during the execution of the input/output operation as well as other pertinent information.


B2500/B3500 Console

The console is an integral part of the processor and consists of a display panel, a control panel and a working surface at table or stand-up height.

The display panel contains two 6-digit display registers made up of NIXIE® tubes for displaying instructions, addresses, or information. The panel also contains back-lighted, fixed messages for the major logical units of the processor and I/O channel indicators.

The control panel consists of a 16-digit keyboard and various control switches for use by the systems operator. With the control panel the operator can:

  1. Start, stop or single-step a program
  2. Initiate a load operation
  3. Examine the instructions, addresses, or data contained in core memory
  4. Enter instructions, addresses, or data into core memory , or alter information presently in core memory.
  5. Activate the emergency power-off cycle.


Two types of load operations are available to the operator: normal and universal.

The normal load is executed by pressing the CL (clear) key and then the LD (load) key on the control panel. This causes the processor to initiate a Read operation from a particular peripheral unit previously established. The input operation reads 100 bytes into a fixed area of memory, compresses the data by stripping off the zone digits, and then branches to the first instruction contained in the data.

The universal load feature allows the operator to enter the desired peripheral unit via the keyboard into absolute address zero. A load instruction, entered through the keyboard and then executed initiates the input operation on the unit entered by the operator. Once initiated, the load operation is the same as the normal load previously described.

Console Printer

For operation with the Master Control Program, a console printer (SPO) is required for communication between the system and the systems operator. The console printer peripheral control contains a single-character buffer since data transmission to and from the console printer is serial-by-bit, whereas it is serial-by-character to main memory.

b2500_b3500.txt · Last modified: 2019/02/03 12:02 by scott
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