Compatibility Notes A.44

The processor may or may not cache Memory Area Table entries during operations.

System Description
V3x0
V4x0
The KERNEL Base/Limit entries are not maintained within the processor
V5x0 The KERNEL Memory Area Table Base/Limit entries are maintained within the processor
compatibility_notes/a44.txt · Last modified: 2011/07/20 12:20 by scott
 
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