Compatibility Notes A.44

The processor may or may not cache Memory Area Table entries during operations.

System Description
The KERNEL Base/Limit entries are not maintained within the processor
V5x0 The KERNEL Memory Area Table Base/Limit entries are maintained within the processor
compatibility_notes/a44.txt · Last modified: 2011/07/20 12:20 by scott
Except where otherwise noted, content on this wiki is licensed under the following license: CC Attribution-Noncommercial-Share Alike 3.0 Unported
Recent changes RSS feed Donate Powered by PHP Valid XHTML 1.0 Valid CSS Driven by DokuWiki