Instruction Set (Part 1)

Opcode Instruction Opcode Instruction Opcode Instruction Opcode Instruction
00 Reserved 20 No Operation (NOP) 40 Bit Zero Test (BZT) 60 Lock (LOK)
01 Two Address Add (INC) 21 Branch If less (LSS) 41 Bit One Test (BOT) 61 Adjust Stack Pointer (ASP)
02 Three Address Add (ADD) 22 Branch If Equal (EQL) 42 Logical AND (AND) 62 Hypercall (HCL)
03 Two Address Subtract (DEC) 23 Branch if Less than or Equal (LEQ) 43 Logical OR (ORR) 63 Return (RET)
04 Three Address Subtract (SUB) 24 Branch if Greater (GTR) 44 Logical NOT (NOT) 64 Search Linked List (SLT)
05 Multiply (MPY) 25 Branch if not equal (NEQ) 45 Compare Alpha (CPA) 65 Write Hardware Register (WHR)
06 Divide (DIV) 26 Branch if Greater than or Equal (GEQ) 46 Compare Numeric (CPN) 66 Search Table (STB)
07 Reserved 27 Branch Unconditionally (BUN) 47 Set Mode Flags (SMF) 67 Load Index Register (LIX)
08 Move Data (MVD) 28 Branch on Overflow (OFL) 48 Halt Breakpoint (HBK) 68 Store Index Register (SIX)
09 Move Links (MVL) 29 Halt Branch (HBR) 49 Edit (EDT) 69 Initialize Lock Structure (ILS)
0A Reserved 2A Branch if Null (NUL) 4a Reserved 6A Move Lock Structure (MLS)
0B Reserved 2B Branch if Greater than or Null (GTN) 4B Reserved 6B Reserved
0C Reserved 2C Reserved 4C Reserved 6C Reserved
0D Reserved 2D Reserved 4D Reserved 6D Reserved
0E Reserved 2E Reserved 4E Reserved 6E Reserved
0F Reserved 2F Reserved 4F Reserved 6F Reserved
10 Move Alphanumeric (MVA) 30 Branch Communicate (BCT) 50 Integer Add (IAD) 70 Real Add (RAA))
11 Move Numeric (MVN) 31 Enter (NTR) 51 Integer Add and Store (IAS) 71 Real And and Store (RAS))
12 Move Words (MVW) 32 Exit (EXT) 52 Integer Subtract (ISU) 72 Real Subtract (RSU)
13 Move Words and Clear (MVC) 33 Bit Reset (BRT) 53 Integer Subtract and Store (ISS) 73 Real Subtract and Store (RSS)
14 Move Repeat (MVR) 34 Bit Set (BST) 54 Integer Multiply (IMU) 74 Real Multiply (RMU)
15 Translate (TRN) 35 Virtual Enter (VEN) 55 Integer Multiply and Store (IMS) 75 Real Multiply and Store (RMS)
16 Scan Delimiter Equal (SDE) 36 Reserved 56 Reserved 76 Real Divide (RDV)
17 Scan Delimiter Unequal (SDU) 37 Search Linked List (SLL) 57 Integer Memory Increment (IMI) 77 Real Divide and Store (RDS)
18 Scan Zone Equal (SZE) 38 Search Linked List Delink (SLD) 58 Integer Load (ILD) 78 Real Load (RLD)
19 Scan Zone Unequal (SZU) 39 Search (SEA) 59 Integer Store (IST) 79 Real Store (RST)
1A Reserved 3A Reserved 5A Reserved 7A Reserved
1B Reserved 3B Reserved 5B Reserved 7B Reserved
1C Reserved 3C Reserved 5C Reserved 7C Reserved
1D Reserved 3D Reserved 5D Reserved 7D Reserved
1E Reserved 3E Reserved 5E Reserved 7E Reserved
1F Reserved 3F Reserved 5F Reserved 7F Reserved

Instruction Set (Part 2)

Opcode Instruction Opcode Instruction Opcode Instruction Opcode Instruction
80 Obsolete Floating Add (FAD) A0 Move String (MVS) C0 Reserved E0 Reserved
81 Obsolete Floating Subtract (FSU) A1 Compare String (CPS) C1 Reserved E1 Predicted Branch If less (LSS) [T/NT]
82 Obsolete Floating Multiply (FMP) A2 Hash String (HSH) C2 Reserved E2 Predicted Branch If Equal (EQL) [T/NT]
83 Obsolete Floating Divide (FDV) A3 Reserved C3 Reserved E3 Predicted Branch if Less than or Equal (LEQ) [T/NT]
84 Accumulator Manipulate (ACM) A4 Reserved C4 Reserved E4 Predicted Branch if Greater (GTR) [T/NT]
85 Convert I/O (CIO) A5 Reserved C5 Reserved E5 Predicted Branch if not equal (NEQ) [T/NT]
86 Alter Table Entry (ATE) A6 Reserved C6 Reserved E6 Predicted Branch if Greater than or Equal (GEQ) [T/NT]
87 Measurement Op (MOP) A7 Reserved C7 Reserved E7 Reserved
88 Decimal to Binary (D2B) A8 Reserved C8 Reserved E8 Reserved
89 Binary To Decimal (B2D) A9 Reserved C9 Reserved E9 Reserved
8A Interprocessor Communicate (IPC) AA Reserved 4a Reserved EA Predicted Branch if Null (NUL) [T/NT]
8B Idle Processor (IDL) AB Fail (BAD) CB Reserved EB Predicted Branch if Greater than or Null (GTN) [T/NT]
8C Reserved AC Reserved CC Reserved EC Reserved
8D Reserved AD Reserved CD Reserved ED Reserved
8E Reserved AE Reserved CE Reserved EE Reserved
8F Reserved AF Reserved CF Reserved EF Reserved
90 Kernel Call (KER)
Interrupt (INT) [Obsolete] ]]\\ [[instructions:bre|Branch Reinstate (BRE) [Obsolete]
B0 Reserved D0 Reserved F0 Reserved
91 Pick I/O Queue (PIQ)
Scan Result Descriptor (SRD) [Obsolete]
B1 Predicted Branch If less (LSS) [NT/T ] D1 Reserved F1 Predicted Branch If less (LSS) [T/T]
92 Read Address (RAD) [Obsolete] B2 Predicted Branch If Equal (EQL) [NT/T] D2 Reserved F2 Predicted Branch If Equal (EQL) [T/T]
93 Branch Reinstate Virtual (BRV) B3 Predicted Branch if Less than or Equal (LEQ) [NT/T] D3 Reserved F3 Predicted Branch if Less than or Equal (LEQ) [T/T]
94 Start Physical I/O (SPIO)
Initiate I/O (IIO) [Obsolete]
B4 Predicted Branch if Greater (GTR) [NT/T] D4 Reserved F4 Predicted Branch if Greater (GTR) [T/T]
95 Read Date/Time (RDT) B5 Predicted Branch if not equal (NEQ) [NT/T] D5 Reserved F5 Predicted Branch if not equal (NEQ) [T/T]
96 Read and Clear Timer (RCT) [Obsolete] B6 Predicted Branch if Greater than or Equal (GEQ) [NT/T] D6 Reserved F6 Predicted Branch if Greater than or Equal (GEQ) [T/T]
97 Set Time (STT) B7 Reserved D7 Reserved F7 Reserved
98 I/O Complete (IOC)
Redlight (RED) [Obsolete]
B8 Reserved D8 Reserved F8 Reserved
99 System Status (SST)
Processor Result Descriptor (PRD) [Obsolete]
B9 Reserved D9 Reserved F9 Reserved
9A Reserved BA Predicted Branch if Null (NUL) [NT/T] DA Reserved FA Predicted Branch if Null (NUL) [T/T]
9B Reserved BB Predicted Branch if Greater than or Null (GTN) [NT/T] DB Reserved FB Predicted Branch if Greater than or Null (GTN) [T/T]
9C Reserved BC Reserved DC Reserved FC Reserved
9D Reserved BD Reserved DD Reserved FD Reserved
9E Reserved BE Reserved DE Reserved FE Reserved
9F Reserved BF Reserved DF Reserved FF Reserved
instructions.txt · Last modified: 2014/01/03 07:34 by scott
 
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