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instructions:six [2009/01/21 13:53] (current)
scott created
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 +====== Store Index Registers (SIX)/OP=68 ======
 +
 +==== Format ====
 +
 +^  OP  ^  AF  ^  BF  ^  A  ^
 +
 +''OP = 68''
 +
 +**AF** is the Destination field length.  The length may be indirect but
 +a literal flag will cause an
 +[[faults:invalid_instruction|Invalid Instruction (IEX = 21)]] fault.
 +A value of __00__ represents
 +a default machine dependent length for single register operations, or
 +four times the internal register length when storing the four Mobile Index
 +Registers.  See [[compatibility_notes:a.62|Compatibility Notes A.62]].
 +
 +**BF** specifies the Store Variant and may be specified as an indirect
 +field length.   The following variants may be specified by this
 +instruction after any indirect field length has been resolved.
 +
 +^  VARIANT  ^  BFM  ^
 +| Store Index Register #7  |  7  |
 +| Store Index Register #6  |  6  |
 +| Store Index Register #5  |  5  |
 +| Store Index Register #4  |  4  |
 +| Store Index Register #3  |  3  |
 +| Store Index Register #2  |  2  |
 +| Store Index Register #1  |  1  |
 +| Store Mobile Index Registers (4)  |  0  |
 +
 +The use of all other **BFM** values is reserved and will cause an
 +[[faults:invalid_instruction|Invalid Instruction (IEX = 26)]] fault.
 +
 +**A** is the address of the destination field.
 +Address may be indexed, indirect or extended.  The final address controller
 +must equal **UN** or **SN** or cause an
 +[[faults:invalid_instruction|Invalid Instruction (IEX = 03)]] fault.
 +
 +==== Function ====
 +
 +The Store Index Register instruction provides the memory address **A** of the
 +starting location of either a data field that will be used to store the
 +specified **BFM** Index Register or the starting location of a
 +data field that will be used to store the four 
 +Mobile Index Registers (IX4, IX5, IX6 and IX7).
 +
 +Each Index Register contains a Sign Digit (MSD), a Base Indicant digits
 +(Next MSD) and a machine dependent offset field.  See
 +[[compatibility_notes:a.32|Compatibility Notes A.32]] for valid
 +Base Indicant values and 
 +[[compatibility_notes:a.62|Compatibility Notes A.62]] for the length of
 +the internal registers.
 +
 +If the store of the four Mobile Index Registers is specifed (**BFM** = __0__),
 +**AF** must be equal to __00__ or an
 +[[faults:invalid_instruction|Invalid Instruction (IEX = 25)]] is reported. The
 +length is by default four times the machine dependent length of a single
 +Index Register.  The Address Controller of the source **A** must be **UN** or
 +an [[faults:invalid_instruction|Invalid Instruction (IEX = 03)]] is reported.
 +
 +If the store of a single register is specified (**BFM** <> __0__) and **AF**
 +is equal to __00__, the length is by default the machine dependent length
 +for a single Index Register.  The Address Controller of the source **A**
 +[[faults:invalid_instruction|Invalid Instruction (IEX = 03)]] is reported.
 +
 +If UN data type is specified and the Destination Length **AF** is equal to
 +or greater than the combined length of the offset field and the base
 +indicant field of the specified Index Register, the combined offset/base
 +indicant ffield of the specified Index Register right justified and padded
 +with zero digits, if needed, is written in the destination field.
 +
 +If the Destination Length **AF** is equal or shorter than the Offset
 +field of the specified index register, the offset field is examined for
 +non-zero content.  If the number of significant digits is greater than the
 +Destination field length **AF**, an
 +[[faults:invalid_instruction|Invalid Instruction (IEX = 07)]] fault is
 +reported  and the instruction is terminated without changing memory. Otherwise
 +store the remainder of the offset field right justified with padding of
 +zero digits, if needed.
 +
 +If **SN** data type is specified, examine the sign digit of the specified
 +Index Register.  The most significant digit of the destination field is
 +set to __D__ if the speicified Index Register is negative otherwise it is
 +set to __C__.  The operation on the other fields is performed as described in
 +the **UN** case.
 +
 +==== Comparison Flags ====
 +
 +The [[processor_state:comparison_flags|Comparison Flags]] are set to EQUAL if
 +all of the digits of the offset field of the specified index register are
 +equal to zero.
 +
 +The [[processor_state:comparison_flags|Comparison Flags]] are set to NULL if
 +all of the digits of the offset field of the specified index register are
 +equal to __E__.
 +
 +Otherwise, the [[processor_state:comparison_flags|Comparison Flags]] are set
 +to HIGH if the sign of the specified Index Register is positive or set to
 +LOW if the sign of the specified Index Register is negative.
 +
 +If the store of the four Mobile Index Registers is specified, the
 +[[processor_state:comparison_flags|Comparison Flags]] will remain unchanged.
 +
 +The [[processor_state:overflow_flag|Overflow Flag]] is unchanged by this
 +instruction.
  
instructions/six.txt ยท Last modified: 2009/01/21 13:53 by scott
 
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