Memory Area Tables

A memory area table (MAT) has up to 100 entries that either contain the actual base and limit pair or point, indirectly through copy descriptors, to the actual base and limit pairs for a memory area.

Each ET entry includes the address of a MAT and the number of entries in that table. Each task, when running, has one of its MATs loaded into the hardware. This is called the local addressing environment.

A task can have up to eight memory areas in its local addressing environment at any one time, and its local addressing environment is defined by an executable Memory Area Table. An executable Memory Area Table contains eight entries, of which Base/Limit #1 references a code memory area (i.e. instructions are fetched from this memory area). An executable Memory Area Table for a task with less than eight memory areas in its local addressing environment will contain Unused entries for those unused Base/Limit pairs in the local addressing environment.

A non-executable memory area table does not necessarily contain a reference to a code memory area in Base/Limit pair #1. It is used for storage of Memory Area descriptors (Base/Limit pairs or copy descriptors) and is usually the target of a copy descriptor in an executable memory area table.

Every task has a User Services Memory Area Table (USMAT). This non-executable Memory Area Table describes the MCP memory areas that contain privileged information about the task. To protect these memory areas from user access, this memory area table is located by the Memory Area Table Address field in the User environment Table entry #0 for the task. Thus to access any of these memory areas via an instruction, the user must specify an environment number of zero, which is illegal except if Privileged Enable is set.

A Memory Area Table entry can have the following MAT entries: Original entry, C copy entry, E copy entry, Memory Area Fault entry and Unused entry.

Some processors require an Alter Table Entry instruction to notify it when a MAT entry is modified.

V3x0/V4x0 Original Entry

Digits Purpose
00-04 Absolute Base Address divided by 1,000 (5UN)
05-09 Absolute Limit Address divided by 1,000 (5UN)
10-13 Software Use
14-19 Memory Area Status Table number
Note: Software must add 10,000 to the desired Base and Limit values to provide absolute memory addresses. This is due to the processor reserving the first 10,000 digits of absolute memory for processor scratchpad and state storage.

V5x0 Original Entry

Digits Purpose
00-05 Absolute Base Address divided by 1,000 (6UN)
06-11 Absolute Limit Address divided by 1,000 (6UN)
12-13 Software Use
14-19 Memory Area Status Table number
Note: The base and limit addresses are mod 1,000 and do not require any adjustment to provide absolute memory addresses.

V3x0, V4x0, V5x0 C-type Copy Descriptor

Digits Purpose
00 Type C
01 Reserved
02-07 Environment Number
08-09 Memory Area Number
10-19 Software Use

V3x0, V4x0, V5x0 E-Type Copy Descriptor

Digits Purpose
00 Type E
01-09 Absolute address of next chained MAT entry
10-19 Software Use

V3x0, V4x0, V5x0 Fault Entry

Digits Purpose
00 Type F
01 Reserved
02-09 Faulted Area Table Address
10-13 Software Use
14-19 Memory Area Status Table number

V3x0, V4x0, V5x0 Unused Entry

Digits Purpose
00 Type B
01-09 Reserved (Must Be Zero)
10-19 Software Use
processor_state/mat.txt · Last modified: 2011/07/23 15:29 by scott
 
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